module pwm_4(
	input clk,  // 时钟信号
    output reg [3:0] wave_PWM,  // 4路PWM方波输出
    output reg [3:0] wave_DIR  // 4路DIR方波输出
 );

// clk为24MHz
parameter CLOCK_FREQ = 24_000_000;
parameter WAVE_FREQ = 1_000;

// 计算计数器最大值
parameter MAX_COUNT = CLOCK_FREQ / ( WAVE_FREQ) - 1;//12000-1
parameter DIR_COUNT = 2000;

// 定义占空比
parameter DUTY_CYCLE_20 = (MAX_COUNT * 20) / 100;
parameter DUTY_CYCLE_40 = (MAX_COUNT * 40) / 100;
parameter DUTY_CYCLE_60 = (MAX_COUNT * 60) / 100;
parameter DUTY_CYCLE_80 = (MAX_COUNT * 80) / 100;
parameter DIR_50 = (DIR_COUNT * 50) / 100;

reg [15:0] counter = 0;  // 计数器
reg [24:0] counter_1 = 0;  // 计数器

always @(posedge clk) begin
    if (counter < MAX_COUNT) begin
        counter <= counter + 1;
    end else begin
        counter <= 0;
        if (counter_1 < DIR_COUNT) begin
        	counter_1 <= counter_1+1;
        end else begin
        	counter_1<=0;
        end
    end
    // 生成四路方波
    wave_PWM[0] <= (counter < DUTY_CYCLE_20) ? 1'b1 : 1'b0;
    wave_PWM[1] <= (counter < DUTY_CYCLE_40) ? 1'b1 : 1'b0;
    wave_PWM[2] <= (counter < DUTY_CYCLE_60) ? 1'b1 : 1'b0;
    wave_PWM[3] <= (counter < DUTY_CYCLE_80) ? 1'b1 : 1'b0;
    wave_DIR[0] <= (counter_1 < DIR_50) ? 1'b1 : 1'b0;
    wave_DIR[1] <= (counter_1 < DIR_50) ? 1'b1 : 1'b0;
    wave_DIR[2] <= (counter_1 < DIR_50) ? 1'b1 : 1'b0;
    wave_DIR[3] <= (counter_1 < DIR_50) ? 1'b1 : 1'b0;
    
end

endmodule
